1. Field of the Invention
The present invention relates to an output driver circuit, and more particularly to an output driver circuit for outputting internal data from a chip in a dynamic random access memory (DRAM) memory device to the outside of the chip.
2. Description of the Related Art
Semiconductor devices use an output driver circuit to output internal data from a chip thereof to the outside of the chip through an output terminal, that is, an output pad.
Such an output driver circuit includes a push-pull driver. Important functions of such a push-pull driver are to adjust the driving strength thereof to a desired level, and to control the slew rate of an output signal.
“Driving strength” is a force for driving an output signal toward a particular voltage level (for example, level of supply voltage or ground voltage). When the driving strength is higher, the output signal has a voltage level more approximate to the particular voltage level. Such a driving strength may be a pull-up driving strength or a pull-down driving strength. The pull-up driving strength is a force for driving an output signal toward a high voltage level, for example, a supply voltage level, whereas the pull-down driving strength is a force for driving an output signal toward a low voltage level, for example, a ground voltage level. In order to control the voltage level of a signal outputted from an output driver to a desired level, it is necessary to adjust the driving strength of the output driver.
“Slew rate” means a variation rate of the voltage level of an output signal, so that it may be considered as a gradient of voltage to time. Such a slew rate may be a rising slew rate or a falling slew rate. The rising slew rate represents the gradient of an output voltage, the level of which is transited from a low level to a high level. On the other hand, the falling slew rate represents the gradient of an output voltage, the level of which is transited from a high level to a low level. At a higher slew rate, the gradient of the output voltage is sharper. In other words, the level of the output voltage is abruptly varied within a short time.
Where an output push-pull driver exhibits a high slew rate, large noise current is generated, even though there is an advantage in terms of data skew. On the other hand, a low slew rate causes an increase in the amount of data skew, even through there is a reduction in noise current. Accordingly, it is necessary to appropriately adjust the slew rate of such an output push-pull driver to a desired value. For instance, in association with double data rate (DDR) II synchronous DRAMs (SDRAMs), standard values of slew rates of output drivers have been established, and strictly managed.
DDR SDRAM was introduced as a substitute for SDRAM in accordance with a new standard scheme to overcome limitations of SDRAM caused by the continuously increased bus speed. Such a DDR SDRAM is approximately similar to a standard SDRAM in terms of operation. However, the DDR SDRAM performs transmission two times per cycle (at rising and falling edges of a clock signal) to achieve a double increase in bandwidth.
Meanwhile, such a DDR SDRAM technique advanced to development of a DDR II SDRAM. For an application thereof to such a DDR II SDRAM, output driver circuits additionally have an off-chip driver (OCD) function to perform an increase or decrease in output driving strength in a step-wise fashion so that adjustment of impedance is achieved in accordance with such output driving strength control. The purpose of such an OCD function for performing control of output driving strength in an output driver circuit is to achieve impedance matching of the output driver circuit to a data output (Dout) signal representing internal data of a memory device, to which the output driver circuit is applied. Hereinafter, this operation will be described in brief.
A pre-driver outputs a plurality of data signals, based on the internal data, that is, the Dout signal. Two of the data signals are applied to respective gates of pull-up-driving and pull-down-driving switch elements, which may be PMOS and NMOS transistors. Another two of the data signals are applied to an OCD pre-driver. In addition to the latter two data signals, the OCD pre-driver receives control signals generated from a control unit of the memory device in accordance with coding information of the internal data. Based on the received signals, the OCD pre-driver generates a plurality of up-driving control signals for control of up-driving impedance, and a plurality of down-driving control signals for control of down-driving impedance. The up-driving and down-driving control signals from the OCD pre-driver are inputted to a push-pull driver, which also receives the data signal from the pre-driver. Based on the received signals, the push-pull driver generates an output signal having a predetermined strength. In this case, the up-driving and down-driving control signals control ON/OFF of the pull-up-driving and pull-down-driving switch elements in the push-pull driver, thereby controlling the impedance of an output driver, that is, the push-pull driver.
However, such a conventional output driver circuit has a problem in that it is impossible to satisfy requirements of characteristics associated with slew rate due to the addition of the OCD function. That is, since the internal data outputted from the memory device via the level shifters is inputted to a new circuit arrangement, that is, the OCD pre-driver, in accordance with the DDR II technique, so that the internal data is processed in accordance with the function of the OCD pre-driver, an increase in current load occurs inevitably. In order to cope with the increased current load, the level shifters inevitably use PMOS and NMOS transistors having increased capacities and sizes. However, such increased capacities of the PMOS and NMOS transistors may cause an excessive increase or decrease in slew rate in the output driver. For this reason, there may be a problem in that it is impossible to satisfy upper and lower limits required for desired characteristics of products in association with slew rate. In particular, such a problem is more remarkable when an increase in slew rate occurs due to increased capacities of the PMOS transistors of the level shifters while exceeding the upper limit required for desired characteristics in association with slew rate.
The following Table 1 describes measured values of slew rate in the conventional output driver circuit. Referring to Table 1, it can be seen that the measured maximum values exceed 4.5 V/ns, which is an upper limit prescribed in association with slew rate in specifications prescribing requirements of characteristics. It can also be seen that, although the measured minimum values are not below 1.5 V/ns, which is a lower limit prescribed in association with slew rate in the specifications, it is approximate to the lower limit, so that the circuit exhibits very unstable operation characteristics.
TABLE 1Slew RateMinimum ValueTypical ValueMaximum ValueUp-Slew-Rate 1.5 Vn/ns3.1 Vn/ns5.1 Vn/nsDown-Slew-Rate1.65 Vn/ns3.1 Vn/ns5.7 Vn/ns